OpenAI Used Its Own LLMs to Design the Jalapeño Chip

How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

OpenAI presented its Jalapeño chip at ISSCC 2026, a 4×4 AI accelerator array whose RTL design was assisted by its own LLMs. Engineers used the models to write Verilog, fix timing, and debug, and the chip taped out successfully. The article doesn't disclose performance numbers but notes design efficiency gains—some modules went from weeks to days. I'd temper expectations: this is an internal toolchain demo, not automated chip design.

Why it matters: OpenAI used its own LLMs to write Verilog, fix timing, and debug, resulting in a taped-out chip with some module dev cycles cut from weeks to days. No performance benchmarks are given, so it's far from 'AI-designed chips,' but it's a substantive internal toolchain demo.