Reiner Pope – Chip Design from the Bottom Up

Reiner Pope – Chip design from the bottom up

Dwarkesh Patel interviews MatX CEO Reiner Pope on chip design, starting with a 4-bit multiply and 8-bit accumulate example that uses 16 AND gates, then covering systolic arrays, pipeline registers, FPGAs versus ASICs, cache versus scratchpad, and why GPU cores are smaller than CPU cores.

Why it matters: Dwarkesh’s MatX CEO interview clears HKR-H/K/R with a bottom-up hardware hook, concrete mechanisms, and compute-cost resonance. It is educational rather than breaking news, so it sits in the 72–77 band.